The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further scaling down or micro-miniaturization of the physical dimensions of the circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, resulting in several problems.
One such problem is copper contamination at the backside surface of silicon wafers during TSV exposure by backgrind and reactive ion etch (RIE). The TSV exposure and RIE can cause copper ion migration into active device regions. This issue is especially problematic after wafer thinning.
A need therefore exists for methodology enabling formation of devices including TSVs with wafer backside protection from copper contamination, and the resulting device.